• Office Address: Min H. Kao Building, Room 319 and 401-C
• Phone: 865-974-3132
• Fax: 865-974-5483
• E-mail: garose@utk.edu

Education

• PhD in Electrical Engineering, University of Virginia, Charlottesville, VA, August 2006
• MS in Electrical Engineering, University of Virginia, Charlottesville, VA, May 2003
• BS in Computer Engineering, Virginia Tech, Blacksburg, VA, May 2001

Garrett S. Rose is a professor of electrical engineering and computer science at UT where his research is focused in the areas of nanoelectronic circuit design, neuromorphic computing and hardware security.

Prior to joining the University of Tennessee, Rose was a Senior Electronics Engineer with the Air Force Research Laboratory (AFRL), Information Directorate, Rome, NY from July 2011. While with AFRL, he led a variety of research efforts in the areas of hardware security and nanocomputing. As with his current research, these efforts were particularly focused on understanding potential security vulnerabilities and strengths in nanoelectronic computing systems. From August 2006 to May 2011, he was an assistant professor in the Department of Electrical and Computer Engineering at the Polytechnic Institute of New York University, Brooklyn, NY where he taught courses in the area of VLSI circuit design. From May 2004 to August 2005 he was with the MITRE Corporation, McLean, VA, involved in the design and simulation of nanoscale circuits and systems.

Rose received his BS degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 2001 and his MS and PhD degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. His PhD dissertation was on the topic of circuit design methodologies for molecular electronic circuits and computing architectures.

Rose is a member of the Association of Computing Machinery, IEEE Circuits and Systems Society and IEEE Computer Society. He serves and has served on Technical Program Committees for several IEEE conferences (including ISCAS, GLSVLSI, NANOARCH) and workshops in the area of VLSI design. In 2010, he was a guest editor for a special issue of the ACM Journal of Emerging Technologies in Computing Systems that presented key papers from the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’09). Since April 2014, he is an associate editor for IEEE Transactions on Nanotechnology.

• Nanoelectric Circuit Design
• Memristors and Memristive Systems
• Emerging Nanoelectronic Computer Architectures
• Hardware Security and Security Implications of Emerging Computing Systems
• Neuromorphic Computing